The process of modifying an integrated circuit (IC) to meet pre-established timing requirements is referred to as “timing closure.” Timing closure can be a challenging task for IC designs because the timing margins shift with changes to process/environment parameters (i.e., process corners). As a result, an optimal implementation for one process corner can fail to meet the timing requirements at another process corner. Numerous place and route and/or other design process iterations may be required to produce a design that meets the pre-established timing requirements (e.g., setup and hold times) for the IC across process corners. Accordingly, timing closure can result in an objectionable increase in the time and cost associated with designing an IC.